Zeinab Seifoori

Seifoori, Zeinab, Behzad Omidi, and Hossein Asadi. "PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era." IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2023).
Seifoori, Zeinab, Hossein Asadi, and Mirjana Stojilovic. "Shrinking FPGA static power via machine learning-based power gating and enhanced routing." IEEE Access 9 (2021): 115599-115619.
Seifoori, Zeinab, Seyedeh Sharareh Mirzargar, and Mirjana Stojilovic. "Closing leaks: Routing against crosstalk side-channel attacks." In Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 197-203. 2020.
Seifoori, Zeinab, Hossein Asadi, and Mirjana Stojilovic. "A machine learning approach for power gating the FPGA routing network." In 2019 International Conference on Field-Programmable Technology (ICFPT), pp. 10-18. IEEE, 2019.
Seifoori, Zeinab, Behnam Khaleghi, and Hossein Asadi. "A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era." In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 1342-1347. IEEE, 2017.
Asadi, Hossein, Elmira Nezamfar, and Zeinab Seifoori. "Configurable logic block for implementing a Boolean function." U.S. Patent 11,088,693, issued August 10, 2021.
Asadi, Hossein, Elmira Nezamfar, and Zeinab Seifoori. "Configurable logic block for implementing a Boolean function." U.S. Patent 11,088,693, issued August 10, 2021.
Seifoori, Zeinab, Zahra Ebrahimi, Behnam Khaleghi, and Hossein Asadi. "Introduction to emerging sram-based fpga architectures in dark silicon era." In Advances in Computers, vol. 110, pp. 259-294. Elsevier, 2018.