K. N. Toosi University

FPGA: Xillinx, Altera – using ISE and Quartus
    Core generator: various filters design
    Microblaze and NIOS
Hardware Description Language (HDL) : Verilog and VHDL
System Level Design : SystemC language – RT, System, and TLM level
Verification Language : System Verilog, PLI.
Simulation tools : ModelSim, MATLAB
Synthesis tools: Synplify, Leonardo, ISE, Quartus
High level synthesis tools : Catapult C
    Design custom hardware for image processing by Catapult C.
Data Acquisition devices : National Instrument (NI)
    Familiar with measurement studio library
    Implementation a software to acquire neuroscience signals
Implementation of digital signal processing components on FPGA and DSP
    Modulation and Demodulation
    Various Filters, FFTs
Implementation of Fast and low power implementation of computation circuits
Implementation a heterogeneous cluster including 16-core processors
    Design accelerators to integrate in homogeneous cluster.
    Designed APIs to synchronize threads such as wait, barrier and so on.
Implementation Data Link Layer of PCI Express for an IP Core on Virtex FPGA.
Verification of Data Link Layer of PCI Express for an IP Core on Virtex FPGA.
Artificial Neural-Network: Hardware Implementation of Brain Emotional Controller