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FPGA: Xillinx, Altera –
using ISE and Quartus
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Core generator: various
filters design
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Microblaze and NIOS
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Hardware Description
Language (HDL) : Verilog and VHDL
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System Level Design :
SystemC language – RT, System, and TLM level
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Verification Language :
System Verilog, PLI.
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Simulation tools :
ModelSim, MATLAB
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Synthesis tools: Synplify,
Leonardo, ISE, Quartus
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High level synthesis tools
: Catapult C
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Design custom hardware for
image processing by Catapult C.
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Data Acquisition devices :
National Instrument (NI)
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Familiar with measurement
studio library
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Implementation a software
to acquire neuroscience signals
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Implementation of digital
signal processing components on FPGA and DSP
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Modulation and Demodulation
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Various Filters, FFTs
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Implementation of Fast and
low power implementation of computation circuits
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Implementation a
heterogeneous cluster including 16-core processors
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Design accelerators to
integrate in homogeneous cluster.
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Designed APIs to
synchronize threads such as wait, barrier and so on.
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Implementation Data Link
Layer of PCI Express for an IP Core on Virtex FPGA.
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Verification of Data Link
Layer of PCI Express for an IP Core on Virtex FPGA.
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Artificial Neural-Network:
Hardware Implementation of Brain Emotional Controller