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www.kntu.a.ir K. N. Toosi University
Masoud DehyadegariAssistant Professor, K. N. Toosi University of Technology
Journal Papers
1. M. Dehyadegari, A. Marongiu, M. R. Kakoee, S. Mohammadi, N. Yazdani, L. Benini, “Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators”, accepted in IEEE transaction on computers, 2014.
2. M. Dehyadegari, S. Mohammadi, N. Yazdani, “Distributed Fair DRAM Scheduling in Network-on-chips Architecture”, Journal of system architecture, vol. 59, no. 7, pp. 543-550, 2013.
3. M. Ebrahimi, H. Tenhunen , M. Dehyadegari, “Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip”, Journal of system architecture, vol. 59, no. 7, pp. 516-527, 2013.
4. M. R. Jamali, A. Arami, M. Dehyadegari, C. Lucas and Z. Navabi, “Emotion on FPGA, Model driven approach”, Expert Systems with Applications, vol. 36, no. 4, pp. 7369-7378, 2009.
5. M. R. Jamali, M. Dehyadegari, A. Arami, C. Lucas and Z. Navabi, “Real Time Embedded Emotional Controller: Implementation of Emotion on FPGA”, Neural Computing & Applications, vol. 19, no. 1, pp. 13-20, 2010.
Conference Papers
1. M. Dehyadegari, A. Marongiu, M. R. Kakoee, S. Mohammadi, N. Yazdani, L. Benini, “A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators”, in Proceedings of international Conference on Embedded Computer Systems (SAMOS), pp. 96-103. July 2012.
2. M. Dehyadegari, S. Mohammadi, N. Yazdani, “Evaluating location of Memory Controller in On-chip Communication Networks”, in Proceedings of International Symposium on Computer Architecture and Digital Systems (CADS), pp. 133-138. May 2012.
3. M. Dehyadegari, M. Daneshtalab, M. Ebrahimi, J. Plosila, S. Mohammadi, “An Adaptive Fuzzy Logic-based Routing Algorithm for Networks-on-Chip,” in Proceedings of International Conference on Adaptive Hardware and Systems (AHS), pp. 208-214, June 2011.
4. M. Kamal, N. Kazemian, A. Kamran, S. A. Hoseini, M. Dehyadegari, H. Noori, “Dual-Purpose Custom Instruction Identification Algorithm based on Particle Swarm Optimization,” in International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 159-166, July 2010.
5. M. R. Jamali, M. Valadbeigi, M. Dehyadegari, Z. Navabi and C. Lucas, “Toward Embedded Emotionally Intelligent System,” in Proceedings of 5th International Symposium on east-west Design & Test, pp. 51-56, 2007.
6. M. Dehyadgari, M. Nickray, A. Afzali-kusha, Z. Navabi, “A New Protocol stack Model for Network on Chip,” in Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures(ISVLSI), pp. 440 – 441, March 2006.
7. M. Dehyadgari, M. Nickray, A. Afzali-kusha, Z. Navabi, “Evaluation of Pseudo Adaptive XY Routing Using an Object Oriented Model for NOC” in Proceedings of International Conference on Microelectronics (ICM), pp.204- 208, 2005.
8. M. Dehyadgari, M. Nickray, A. Afzali-kusha, “Low Power Communication for Network on Chip” International Symposium on Telecommunications, July 2005.
9. M. Nickray, M. Dehyadgari, A. Sobhani, A.Afzali-kusha, “LPPM: Low Power Partitioned Multiplier” The 17th Iranian Conference on Electrical Engineering, 13-15 May. 2005.
10. M. Nickray, M. Dehyadgari, A. Afzali-kusha, “Power and delay optimization for network-on-chip,” in Proceedings of European Conference on Circuit Theory and Design, pp. 273-276, 2005.
11. M. Nickray, M. Dehyadgari, A. Sobhani, A.Afzali-kusha, “Multiplier for Correlative Input Patterns” in Proceedings of International Conference on Microelectronics(ICM), pp. 72–74, 2005.
1. M. Dehyadegari, A. Marongiu, M. R. Kakoee, S. Mohammadi, N. Yazdani, L. Benini, “Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators”, accepted in IEEE transaction on computers, 2014.
2. M. Dehyadegari, S. Mohammadi, N. Yazdani, “Distributed Fair DRAM Scheduling in Network-on-chips Architecture”, Journal of system architecture, vol. 59, no. 7, pp. 543-550, 2013.
3. M. Ebrahimi, H. Tenhunen , M. Dehyadegari, “Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip”, Journal of system architecture, vol. 59, no. 7, pp. 516-527, 2013.
4. M. R. Jamali, A. Arami, M. Dehyadegari, C. Lucas and Z. Navabi, “Emotion on FPGA, Model driven approach”, Expert Systems with Applications, vol. 36, no. 4, pp. 7369-7378, 2009.
5. M. R. Jamali, M. Dehyadegari, A. Arami, C. Lucas and Z. Navabi, “Real Time Embedded Emotional Controller: Implementation of Emotion on FPGA”, Neural Computing & Applications, vol. 19, no. 1, pp. 13-20, 2010.
Conference Papers
1. M. Dehyadegari, A. Marongiu, M. R. Kakoee, S. Mohammadi, N. Yazdani, L. Benini, “A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators”, in Proceedings of international Conference on Embedded Computer Systems (SAMOS), pp. 96-103. July 2012.
2. M. Dehyadegari, S. Mohammadi, N. Yazdani, “Evaluating location of Memory Controller in On-chip Communication Networks”, in Proceedings of International Symposium on Computer Architecture and Digital Systems (CADS), pp. 133-138. May 2012.
3. M. Dehyadegari, M. Daneshtalab, M. Ebrahimi, J. Plosila, S. Mohammadi, “An Adaptive Fuzzy Logic-based Routing Algorithm for Networks-on-Chip,” in Proceedings of International Conference on Adaptive Hardware and Systems (AHS), pp. 208-214, June 2011.
4. M. Kamal, N. Kazemian, A. Kamran, S. A. Hoseini, M. Dehyadegari, H. Noori, “Dual-Purpose Custom Instruction Identification Algorithm based on Particle Swarm Optimization,” in International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 159-166, July 2010.
5. M. R. Jamali, M. Valadbeigi, M. Dehyadegari, Z. Navabi and C. Lucas, “Toward Embedded Emotionally Intelligent System,” in Proceedings of 5th International Symposium on east-west Design & Test, pp. 51-56, 2007.
6. M. Dehyadgari, M. Nickray, A. Afzali-kusha, Z. Navabi, “A New Protocol stack Model for Network on Chip,” in Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures(ISVLSI), pp. 440 – 441, March 2006.
7. M. Dehyadgari, M. Nickray, A. Afzali-kusha, Z. Navabi, “Evaluation of Pseudo Adaptive XY Routing Using an Object Oriented Model for NOC” in Proceedings of International Conference on Microelectronics (ICM), pp.204- 208, 2005.
8. M. Dehyadgari, M. Nickray, A. Afzali-kusha, “Low Power Communication for Network on Chip” International Symposium on Telecommunications, July 2005.
9. M. Nickray, M. Dehyadgari, A. Sobhani, A.Afzali-kusha, “LPPM: Low Power Partitioned Multiplier” The 17th Iranian Conference on Electrical Engineering, 13-15 May. 2005.
10. M. Nickray, M. Dehyadgari, A. Afzali-kusha, “Power and delay optimization for network-on-chip,” in Proceedings of European Conference on Circuit Theory and Design, pp. 273-276, 2005.
11. M. Nickray, M. Dehyadgari, A. Sobhani, A.Afzali-kusha, “Multiplier for Correlative Input Patterns” in Proceedings of International Conference on Microelectronics(ICM), pp. 72–74, 2005.